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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
Register Name: SYNC1
Register Description: DS21Q55 TSYNC Pin Source
Register Offset: 0x0015
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
T4SRC
0
2
T3SRC
0
1
T2SRC
0
0
T1SRC
0
Bit 0: DS21Q55 Port 1 TSYNC Source (T1SRC)
0 = TSYNC 1 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 1 with RSYNC 1
Bit 1: DS21Q55 Port 2 TSYNC Source (T2SRC)
0 = TSYNC 2 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 2 with RSYNC 2
Bit 2: DS21Q55 Port 3 TSYNC Source (T3SRC)
0 = TSYNC 3 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 3 with RSYNC 3
Bit 3: DS21Q55 Port 4 TSYNC Source (T4SRC)
0 = TSYNC 4 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 4 with RSYNC 4
Note: When driving TSYNCx with RSYNCx the corresponding DS21Q55 port should be configured such that
TSYNCx is an input (IOCR1.1 = 0) and RSYNCx is an output (IOCR1.4 = 0).
Register Name: SYNC2
Register Description: DS21Q55 TSSYNC Pin Source
Register Offset: 0x0016
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
T4SRC
0
2
T3SRC
0
1
T2SRC
0
0
T1SRC
0
Bit 0: DS21Q55 Port 1 TSSYNC Source (T1SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 1 with RSYNC 1
Bit 1: DS21Q55 Port 2 TSSYNC Source (T2SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 2 with RSYNC 2
Bit 2: DS21Q55 Port 3 TSSYNC Source (T3SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 3 with RSYNC 3
Bit 3: DS21Q55 Port 4 TSSYNC Source (T4Source)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 4 with RSYNC 4
Note: When driving TSSYNCx with RSYNCx the corresponding DS21Q55 port should be configured such that
RSYNCx is an output (IOCR1.4 = 0).
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